1. Field of Art
The disclosure generally relates to the emulation of designs, and more specifically to routing connections between units of a design through one or more interface field programmable gate arrays (FPGAs) of an emulator.
2. Description of the Related Art
Emulators have been developed to assist circuit designers in designing and debugging highly complex integrated circuit designs, such as a system on a chip (SOC). An emulator includes multiple field programmable gate arrays (FPGAs) that together can imitate the operations of a design under test (DUT). By using an emulator to imitate the operations of a DUT, designers can verify whether a DUT complies with various design requirements prior to fabrication.
A DUT typically includes multiple intellectual property (IP) units, such as a central processing unit (CPU), graphics processing unit (GPU), and peripheral component interface (PCI). In an emulator one or more FPGAs are configured emulate each of the units. For example, a first group of FPGAs may emulate the CPU and another group of FPGAs may emulate the GPU. During emulation, signals exchanged between the FPGAs of two IP units may be routed through the FPGAs of another IP unit, for example, if there are no direct connections between the FPGAs of the two IP units. As a result, if a change is made to either of the two IP units (e.g., during debugging), the FPGAs of all three IP units may have to be reconfigured. In an emulation environment that includes many IP units, this may mean hundreds of FPGAs being reconfigured which is very time consuming and inefficient.